System Interface

The following signals are required from the CPU core in order to interface to the CDM module:

Signal Width Direction Description
du_stall_i 1 CDM->CPU Logic ‘1’ causes CPU to stall
du_stall_o 1 CPU->CDM Indicates CPU has reached breakpoint condition
du_stb_i 1 CDM->CPU Access to the core debug interface
du_ack_o 1 CPU->CDM Complete access to the core
du_adr_i 16 CDM->CPU Address of CPU register to be read or written
du_we_i 1 CDM->CPU Write cycle when true, read cycle when false
du_dat_i 32 CDM->CPU Write data
du_dat_o 32 CPU->CDM Read data

Reference: https://opencores.org/usercontent/doc/1242694069 (Section 2.2.1)