osdtestlib.debug_interconnect

Access the Debug Interconnect in OSD

copyright:Copyright 2017-2018 by the Open SoC Debug team
license:MIT, see LICENSE for details.
class osdtestlib.debug_interconnect.AliasBusDriver(entity, name, clock, signal_aliases={})

Extension of the cocotb.BusDriver to support aliases for signal names

class osdtestlib.debug_interconnect.NocDiWriter(entity, clock, signal_aliases={})

Writer for the OSD Debug Interconnect implemented as NoC

send_packet

Transmit a complete packet to a chosen debug module

Parameters:packet – debug interconnect packet
class osdtestlib.debug_interconnect.NocDiReader(entity, clock, signal_aliases={})

Reader for the OSD Debug Interconnect implemented as NoC

read_timeout_cycles = 1000
receive_packet

Receive a packet from the debug interconnect

Parameters:set_ready (bool) – Set the ready signal to tell the DUT we can receive data. If set to True, this function will handle the ready signal. If set to False, you must set the ready signal yourself. This mode is useful for toggling the ready signal during the receive operation to achieve greater coverage of edge cases.
Returns:DiPacket
class osdtestlib.debug_interconnect.DiPacket

A single debug interconnect packet

class TYPE

Packet types

REG = 0
PLAIN = 1
EVENT = 2
RESERVED = 4
class TYPE_SUB

Packet subtypes

REQ_READ_REG_16 = 0
REQ_READ_REG_32 = 1
REQ_READ_REG_64 = 2
REQ_READ_REG_128 = 3
REQ_WRITE_REG_16 = 4
REQ_WRITE_REG_32 = 5
REQ_WRITE_REG_64 = 6
REQ_WRITE_REG_128 = 7
RESP_READ_REG_SUCCESS_16 = 8
RESP_READ_REG_SUCCESS_32 = 9
RESP_READ_REG_SUCCESS_64 = 10
RESP_READ_REG_SUCCESS_128 = 11
RESP_READ_REG_ERROR = 12
NOT_DEFINED = 13
RESP_WRITE_REG_SUCCESS = 14
RESP_WRITE_REG_ERROR = 15
class BASE_REG

Base register addresses

MOD_VENDOR = 0
MOD_TYPE = 1
MOD_VERSION = 2
MOD_CS = 3
MOD_EVENT_DEST = 4
class SCM_REG

SCM Register map

SYSTEM_VENDOR_ID = 512
SYSTEM_DEVICE_ID = 513
NUM_MOD = 514
MAX_PKT_LEN = 515
SYSRST = 516
class MAM_REG

MAM Register map

AW = 512
DW = 513
REGIONS = 514
flits

The data words this packet consists of

Getter:Get the flits this packet consists of
Setter:Take flits and set the packet contents based on it
set_contents(dest, src, type, type_sub, payload)

Populate the data fields of a packet

Parameters:
  • dest – DI address of the target module
  • src – DI address of the sending module
  • type – packet type
  • type_sub – packet subtype
  • payload – payload
equal_to(dut, other_packet, mask=None)

Compares a packet with another packet and outputs if both are equal

Parameters:
  • dut – device under test
  • other_packet – debug interconnect packet which this packet is compared to
  • mask – list of boolean variables indicating which flits of the payload are to be ignored
Returns:

True if the packets are equal (modulo the mask), False otherwise
class osdtestlib.debug_interconnect.RegAccess(dut, reader=None, writer=None)

Access registers of debug modules

read_register

Read a value from a specified register and return the read value to the user.

Parameters:
  • dest – DI address of the target module.
  • src – DI address of the sending module.
  • word_width – choose between 16, 32, 64 and 128 bit register access.
  • regaddr – address of the register the value is to be read from.
Returns:

Value read from the register
write_register

Write a new value into a register specified by the user and read the response to tell the user if the write process was successful

Parameters:
  • dest – id of the target module.
  • src – id of the sending module.
  • word_width – choose between 16, 32, 64 and 128 bit register access.
  • regaddr – address of the register the new value will be written to.
  • value – value to write to the register
assert_reg_value

Assert that a register contains an expected value

test_base_registers

Test the functionality of the base registers